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M80C196KB 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER
Military
Y Y Y Y Y Y Y Y Y
Y
232 Byte Register File Register-to-Register Architecture 28 Interrupt Sources 16 Vectors 2 3 ms 16 x 16 Multiply (12 MHz) 4 0 ms 32 16 Divide (12 MHz) Powerdown and Idle Modes Five 8-Bit I O Ports 16-Bit Watchdog Timer Dynamically Configurable 8-Bit or 16-Bit Buswidth Available in 68-Lead PGA and 68-Lead Ceramic Quad Flat Pack
Y Y Y Y Y Y Y Y Y
Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Up Down Counter with Capture Pulse-Width-Modulated Output Four 16-Bit Software Timers 10-Bit A D Converter with S H 12 MHz Version M80C196KB Available in Two Product Grades MIL-STD-883 b 55 C to a 125 C (TC) Military Temperature Only (MTO) b 55 C to a 125 C (TC)
The M80C196KB 16-bit microcontroller is a high performance member of the MCS -96 microcontroller family The M80C196KB is pin-for-pin compatible and uses a true superset of the M8096 instructions Intel's CHMOS process provides a high performance processor along with low power consumption To further reduce power requirements the processor can be placed into Idle or Powerdown Mode Bit byte word and some 32-bit operations are available on the M80C196KB With a 12 MHz oscillator a 16-bit addition takes 0 66 ms and the instruction times average 0 5 ms to 1 5 ms in typical applications Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the timer or up down counter Also provided on-chip are an A D converter with Sample and Hold serial port watchdog timer and a pulsewidth-modulated output signal
271089 - 1
Figure 1 M80C196KB Block Diagram
October 1993
Order Number 271089-006
M80C196KB
ARCHITECTURE
The M80C196KB is a member of the MCS -96 family and as such has the same architecture and uses the same instruction set as the M8096 Many new features have been added on the M80C196KB including CPU FEATURES Divide by 2 instead of divide by 3 clock for 1 5X performance Faster instructions especially indexed indirect data operations 2 33 ms 16 c 16 multiply with 12 MHz clock (was 6 25 ms) on the 8096 Faster interrupt response (almost twice as fast as 8096) Powerdown and Idle Modes 6 new instructions including Compare Long and Block Move 8 new interrupt vectors 6 new interrupt sources PERIPHERAL FEATURES SFR Window switching allows read-only registers to be written and vice-versa Timer2 can count up or down by external selection Timer2 has an independent capture register HSO line events are stored in a register HSO has CAM Lock and CAM Clear commands New Baud Rate values are needed for serial port higher speeds possible in all modes Double buffered serial port transmit register Serial Port Receive Overrun and Framing Error Detection PWM has a Divide-by-2 Prescaler
2
M80C196KB
NEW INSTRUCTIONS
PUSHA PUSHes the PSW IMASK IMASK1 and WSR (Used instead of PUSHF when new interrupts and registers are used ) assembly language format PUSHA object code format k 11110100 l bytes 1 states on-chip stack 12 off-chip stack 18 POPA POPs the PSW IMASK IMASK1 and WSR (Used instead of POPF when new interrupts and registers are used ) assembly language format POPA object code format k 11110101 l bytes 1 states on-chip stack 12 off-chip stack 18 IDLPD Sets the part into Idle or Powerdown Mode assembly language format IDLPD bytes 2 states legal key 8 illegal key 25 DJNZW Decrement Jump Not Zero using a Word counter assembly language format DJNZW wreg cadd object code format k 11100001 l k wreg lk disp l bytes 3 states jump not taken 6 jump taken 10 CMPL Compare 2 long direct values assembly language format CMPL bytes 3 states 7 BMOV Block move using 2 auto-incrementing pointers and a counter assembly language format BMOV bytes 3 states PTRS CNTREG Lreg wreg DST SRC Lreg Lreg key (key e 1 for Idle key e 2 for Powerdown ) object code format k 11110110 lk key l
object code format k 11000101 lk src Lreg lk dst Lreg l
object code format k 11000001 lk wreg lk Lreg l internal internal 8 per transfer a 6 external internal 11 per transfer a 6 external external 14 per transfer a 6
3
M80C196KB
SFR OPERATION
All of the registers that were present on the M8096 work the same way as they did except that the baud rate value is different The new registers shown in the memory map control new functions The most important new register is the Window Select Register (WSR) which allows reading of the formerly write-only registers and vice-versa Using the WSR is described later in this data sheet
4
M80C196KB
PACKAGING
The M80C196KB is available in a ceramic pin grid array shown in Figure 2 and a leaded ceramic quad pack shown in Figure 3 A comparison of the pinouts for both of these package types is shown in Tables 1a - 1c
271089 - 2
Figure 2 Pin Grid Array Pinout 5
M80C196KB
271089 - 3
Figure 3 68-Lead Ceramic Quad Flat Pack Pinout Table 1a M80C196KB Pinout
PGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Signal ACH7 P0 7 ACH6 P0 6 ACH2 P0 2 ACH0 P0 0 ACH1 P0 1 ACH3 P0 3 NMI EA VCC VSS XTAL1 XTAL2 CLKOUT BUSWIDTH INST ALE ADV RD AD0 P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 AD5 P3 5 PGA 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Signal AD6 P3 6 AD7 P3 7 AD8 P4 0 AD9 P4 1 AD10 P4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 T2CLK P2 3 READY T2RST P2 4 AINC BHE WRH WR WRL PWM P2 5 T2CAPTURE P2 7 PACT VPP VSS HS0 3 HS0 2 T2UP-DN P2 6 P1 7
in PGA Pin Order
PGA 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal P1 6 P1 5 HSO 1 HSO 0 HSO 5 HSI 3 HSO 4 HSI 2 HSI 1 HSI 0 P1 4 P1 3 P1 2 P1 1 P1 0 TXD P2 0 RXD P2 1 RESET EXTINT P2 2 VSS VREF ANGND ACH4 P0 4 ACH5 P0 5
6
M80C196KB
Table 1b M80C196KB Pinout
CQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Signal VCC EA NMI ACH3 P0 3 ACH1 P0 1 ACH0 P0 0 ACH2 P0 2 ACH6 P0 6 ACH7 P0 7 ACH5 P0 5 ACH4 P0 4 ANGND VREF VSS EXTINT P2 2 RESET RXD P2 1 TXD P2 0 P1 0 P1 1 P1 2 P1 3 P1 4 CQFP 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 HSI 0 HSI 1 HSO 4 HSI 2 HSO 5 HSI 3 HSO 0 HSO 1 P1 5 P1 6 P1 7 T2UP-DN P2 6 HSO 2 HSO 3 VSS VPP Signal
in CQFP Pin Order
CQFP 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Signal AD13 P4 5 AD12 P4 4 AD11 P4 3 AD10 P4 2 AD9 P4 1 AD8 P4 0 AD7 P3 7 AD6 P3 6 AD5 P3 5 AD4 P3 4 AD3 P3 3 AD2 P3 2 AD1 P3 1 AD0 P3 0 RD ALE ADV INST BUSWIDTH CLKOUT XTAL2 XTAL1 VSS
T2CAPTURE P2 7 PACT PWM P2 5 WR WRL BHE WRH T2RST P2 4 AINC READY T2CLK P2 3 AD15 P4 7 AD14 P4 6
Table 1c M80C196KB Pinout
Signal ACH0 P0 0 ACH1 P0 1 ACH2 P0 2 ACH3 P0 3 ACH4 P0 4 ACH5 P0 5 ACH6 P0 6 ACH7 P0 7 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 TXD P2 0 RXD P2 1 EXTINT P2 2 T2CLK P2 3 T2RST P2 4 AINC PWM P2 5 T2UP-DN P2 6 PGA 4 5 3 6 67 68 2 1 59 58 57 56 55 48 47 46 60 61 63 34 36 39 45 CQFP 6 5 7 4 11 10 8 9 19 20 21 22 23 30 31 32 18 17 15 44 42 39 33 Signal
in Signal Order
PGA CQFP 38 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 28 29 34 35 26 27 Signal HSI 0 HSI 1 RD WR WRL BHE WRH BUSWIDTH ALE ADV EA INST READY NMI RESET XTAL1 XTAL2 CLKOUT ANGND VREF VPP VCC VSS VSS VSS PGA 54 53 17 38 37 14 16 8 15 35 7 62 11 12 13 66 65 41 9 10 42 64 CQFP 24 25 61 40 41 64 62 2 63 43 3 16 67 66 65 12 13 37 1 68 36 14
T2CAPTURE P2 7 PACT 40 AD0 P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 AD5 P3 5 AD6 P3 6 AD7 P3 7 AD8 P4 0 AD9 P4 1 AD10 P4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 HSI 2 HSO 5 HSI 3 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 50 49 44 43 52 51
7
M80C196KB
PIN DESCRIPTIONS
Symbol VCC VSS VREF Main supply voltage (5V) Digital circuit ground (0V) There are three VSS pins all of which must be connected Reference voltage for the A D converter (5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference ground for the A D converter Must be held at nominally the same potential as VSS Timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC This pin was VBB on the 8X9X-90 parts and is the programming voltage on EPROM part Input of the oscillator inverter and of the internal clock generator Output of the oscillator inverter Output of the internal clock generator The frequency of CLKOUT is frequency It has a 50% duty cycle the oscillator Name and Function
ANGND VPP
XTAL1 XTAL2 CLKOUT RESET
Reset input to the chip Input low for at least 4 state times to reset the chip The subsequent low-to-high transition re- synchronizes CLKOUT and commences a 10-statetime sequence in which the PSW is cleared a byte read from 2018H loads CCR and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH is a 0 an 8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus This pin is the TEST pin on 8X9X-90 parts Systems with TEST tied to VCC do not need to change
BUSWIDTH
8
M80C196KB
PIN DESCRIPTIONS (Continued)
Symbol NMI INST Name and Function A positive transition causes a vector through 203EH Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch EA must be equal to a TTL-low to cause address locations 2000H through 3FFFH to be directed to off-chip memory Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads Write and Write Low output to external memory as selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is activated only during external memory writes Bus High Enable or Write High output to external memory as selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects the bank of memory that is connected to the low byte of the data bus Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is valid only during 16-bit external memory write cycles Ready input to lengthen external memory cycles for interfacing to slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait mode until the next positive transition in CLKOUT occurs with READY high When the external memory is not being used READY has no effect Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them (HSI 2 and HSI 3) are shared with the HSO Unit Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 and HSO 5 Two of them (HSO 4 and HSO 5) are shared with the HSI Unit 8-bit high impedance input-only port Three pins can be used as digital inputs and or as analog inputs to the on-chip A D converter 8-bit quasi-bidirectional I O port 8-bit multi-functional port All of its pins are shared with other functions in the M80C196KB 8-bit bi-directional I O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups
EA ALE ADV
RD WR WRL
BHE WRH
READY
HSI HSO Port 0 Port 1 Port 2 Ports 3 and 4
9
M80C196KB
Instruction Summary
Mnemonic ADD ADDB ADD ADDB ADDC ADDCB SUB SUBB SUB SUBB SUBC SUBCB CMP CMPB MUL MULU MUL MULU MULB MULUB MULB MULUB DIVU DIVUB DIV DIVB AND ANDB AND ANDB OR ORB XOR XORB LD LDB ST STB LDBSE LDBZE PUSH POP PUSHF POPF SJMP LJMP BR indirect SCALL LCALL Operands 2 3 2 2 3 2 2 2 3 2 3 2 2 2 2 2 3 2 2 2 2 2 2 1 1 0 0 1 1 1 1 1 D D Operation (Note 1) Z N Flags C V VT ST Notes
wDaA wBaA DwDaAaC DwDbA DwBbA DwDbAaCb1
DbA
v v
b b b b b b b b b b b b b b b b b b b b b b b b b b b b
u u u u u u u
b b b b
b b b b b b b b b b b b b b b b b b b b b b b b b
wDcA a2wBcA DD DDa1wDcA DDa1wBcA D w(D D a 2) A D a 2 w remainder D w(D D a 1) A D a 1 w remainder D w(D D a 2) A D a 2 w remainder D w(D D a 1) A D a 1 w remainder D w D AND A D w B AND A D w D OR A D w D (ecxl or) A DwA AwD D w A D a 1 w SIGN(A) DwA Da1w0 SP w SP b 2 (SP) w A A w (SP) SP a 2 SP w SP b 2 (SP) w PSW PSW w 0000H I w 0 PSW w (SP) SP w SP a 2 I w PC w PC a 11-bit offset PC w PC a 16-bit offset
DDa2 PCw (A) SP (SP)
2 2 3 3 2 3
u u u u
0 0 0 0
b b b b b b b b b b b b b b b b
0 0 0 0
b b b b b b b b b b b b b b b b b b
34 34
0
0
0
0
0
0
b b b b
b b b b
b b b b
b b b b
b b b b
b b b b
5 5
w SP b 2 w PC PC w PC a 11-bit offset SP w SP b 2 (SP) w PC PC w PC a 16-bit offset
5 5
b
b
b
b
b
b
10
M80C196KB
Instruction Summary (Continued)
Mnemonic RET J (conditional) JC JNC JE JNE JGE JLT JGT JLE JH JNH JV JNV JVT JNVT JST JNST JBS JBC DJNZ DJNZW DEC DECB NEG NEGB INC INCB EXT EXTB NOT NOTB CLR CLRB SHL SHLB SHLL SHR SHRB SHRL SHRA SHRAB SHRAL SETC CLRC Operands 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1 1 1 1 1 1 1 2 2 2 0 0 PC PC Operation (Note 1) Z Flags N C V VT ST
b b b b b b b b b b b b b b b b b b b b b
Notes
w (SP) SP w SP a 2 w PC a 8-bit offset (if taken)
bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbbb bbbb bbbb
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 56 56 5
Jump if C e 1 jump if C e 0 jump if Z e 1 Jump if Z e 0 Jump if N e 0 Jump if N e 1 Jump if N e 0 and Z e 0 Jump if N e 1 or Z e 1 Jump if C e 1 and Z e 0 Jump if C e 0 or Z e 1 Jump if V e 0 Jump if V e 1 Jump if VT e 1 Clear VT Jump if VT e 0 Clear VT Jump if ST e 1 Jump if ST e 0 Jump if Specified Bit e 1 Jump if Specified Bit e 0 D If D D
0 0
bbbbb bbbbb bbbbb bbbbb bbbbb
w
i
Db1 0 then PC
w PC a 8-bit offset u u u
0 0 0 1 0 0 0 0 0 0
b b b b b b b b b b b b
wDb1 Dw0bD DwDa1 D w D D a 2 w Sign (D) D w D D a 1 w Sign (D) D w Logical Not (D) Dw0 C w msb - - - - - lsb w 0 0 x msb - - - - - lsb x C msb x msb - - - - - lsb x C Cw1 Cw0
2 3
u
0 0
bb bb b b
7 7 7
1bb 0bb
b b
11
M80C196KB
Instruction Summary (Continued)
Mnemonic CLRVT RST DI EI NOP SKIP NORML TRAP PUSHA Operands 0 0 0 0 0 0 2 0 1 VT PC Operation (Note 1) Z N
b
Flags C
b
Notes VT 0 0
b b b b b b
V
b
ST
b
w0 w 2080H w 0) w 1) w PC a 1 w PC a 2
b
0
b b b b
0
b b b b
0
b b b b
0
b b b b b b
0
b b b b b b
8
Disable All Interupts (I Enable All Interupts (I PC PC
POPA IDLPD
1 1
w shift count w SP b 2 w PC PC w (2010H) SP w SP-2 (SP) w PSW PSW w 0000H SP w SP-2 (SP) w IMASK1 WSR IMASK1 w 00H IMASK1 WSR w (SP) SP w SP a 2 PSW w (SP) SP w SP a 2
Left shift till msb e 1 D SP (SP) IDLE MODE IF KEY e 1 POWERDOWN MODE IF KEY e 2 CHIP RESET OTHERWISE D-A PTR PTR UNTIL COUNT e 0 HI a
0
b b b
7 9
0
0
0
0
0
0
b
b
b
b
b
b
CMPL BMOV
2 2
u w
LOW a
b b b b b
b b
NOTES 1 If the mnemonic ends in ``B'' a byte operation is performed otherwise a word operation is done Operands D B and A must conform to the alignment rules for the required operand type D and B are locations in the Register File A can be located anywhere in memory 2 D D a 2 are consecutive WORDS in memory D is DOUBLE-WORD aligned 3 D D a 1 are consecutive BYTES in memory D is WORD aligned 4 Changes a byte to word 5 Offset is a 2's complement number 6 Specified bit is one of the 2048 bits in the register file 7 The ``L'' (Long) suffix indicates double-word operation 8 Initiates a Reset by pulling RESET low Software should re-initialize all the necessary registers with code starting at 2080H 9 The assembler will not accept this mnemonic
12
M80C196KB
Instruction Execution State Times (Minimum) (1)
MNEMONIC ADD (3-op) SUB (3-op) ADD (2-op) SUB (2-op) ADDC SUBC CMP ADDB (3-op) SUBB (3-op) ADDB (2-op) SUBB (2-op) ADDCB SUBCB CMPB MUL (3-op) MULU (3-op) MUL (2-op) MULU (2-op) DIV DIVU MULB (3-op) MULUB (3-op) MULB (2-op) MULUB (2-op) DIVB DIVUB AND (3-op) AND (2-op) OR (2-op) XOR ANDB (3-op) ANDB (2-op) ORB (2-op) XORB LD LDB ST STB LDBSE LDBZE BMOV PUSH (int stack) POP (int stack) PUSH (ext stack) POP (ext stack) 6 8 8 11 DIRECT 5 5 4 4 4 4 4 5 5 4 4 4 4 4 16 14 16 14 26 24 12 10 12 10 18 16 5 4 4 4 5 4 4 4 4 4 4 4 IMMED 6 6 5 5 5 5 5 5 5 4 4 4 4 4 17 15 17 15 27 25 12 10 12 10 18 16 6 5 5 5 5 4 4 4 5 5 4 4 6 a 8 per word 7
b
INDIRECT NORMAL 7 10 7 10 68 68 68 68 68 7 10 7 10 68 68 68 68 68 18 16 18 16 28 26 14 12 14 12 20 18 21 19 21 19 31 29 17 15 17 15 23 21 A-INC 8 11 8 11 79 79 79 79 79 8 11 8 11 79 79 79 79 79 19 17 19 17 29 27 15 13 15 13 21 19 22 19 22 19 32 30 18 15 18 15 24 22
INDEXED SHORT 7 10 7 10 68 68 68 68 68 7 10 7 10 68 68 68 68 68 19 17 19 17 29 27 15 12 15 12 21 19 22 20 22 20 32 30 18 16 18 16 24 22 LONG 8 11 8 11 79 79 79 79 79 8 11 8 11 79 79 79 79 79 20 18 20 18 30 28 16 14 16 14 22 20 23 21 23 21 33 31 19 17 19 17 25 23
7 10 68 68 68 7 10 68 68 68 5 5 5 5 8 8 8 8
8 11 79 79 79 8 11 79 79 79 6 6 6 6 8 9 8 8
7 10 68 68 68 7 10 68 68 68 6 6 6 6 9 9 9 9
8 11 79 79 79 8 11 79 79 79 7 7 7 7 10 10 10 10
6 a 11 14 per word 9 12 10 12 11 14 13 15 10 11 12 14 13 13 15 16 10 11 12 14 13 13 15 16 11 12 13 15 14 14 16 17
9
b
Times for (Internal External) Operands NOTE 1 Execution times for instructions accessing external data memory may be one to two states higher depending on the instruction stream being executed In sixteen bit mode the minimum execution state times apply for instructions accessing internal register space Execution times do not reflect eight bit mode or insertion of wait states
13
M80C196KB
Instruction Execution State Times (Continued)
MNEMONIC PUSHF (int stack) POPF (int stack) PUSHA (int stack) POPA (int stack) TRAP (int stack) LCALL (int stack) SCALL (int stack) RET (int stack) CMPL CLR CLRB NOT NOTB NEG NEGB LJMP SJMP BR indirect JNST JST JNH JH JGT JLE JNC JC JNVT JVT JNV JV JGE JLT JNE JE JBC JBS DJNZ DJNZW NORML SHRL SHLL SHRAL SHR SHRB SHL SHLB SHRA SHRAB CLRC SETC DI EI CLRVT NOP RST SKIP IDLPD 7 7 7 4 4 4 4 4 4 4 4 5 6 7 12 12 16 11 11 11 7 3 3 3 MNEMONIC PUSHF (ext stack) POPF (ext stack) PUSHA (ext stack) POPA (ext stack) TRAP (ext stack) LCALL (ext stack) SCALL (ext stack) RET (ext stack) DEC DECB EXT EXTB INC INCB 8 10 18 18 18 13 13 14 3 4 3
8 jump not taken 8 jump not taken 8 jump not taken 8 jump not taken 8 jump not taken 8 jump not taken 8 jump not taken 8 jump not taken 9 jump not taken
jump taken jump taken jump taken jump taken jump taken jump taken jump taken jump taken jump taken
5 9 jump not taken jump taken 5 9 jump not taken jump taken 8 a 1 per shift (9 for 0 shift) 7 a 1 per shift (8 for 0 shift) 7 a 1 per shift (8 for 0 shift) 7 a 1 per shift (8 for 0 shift) 6 a 1 per shift (7 for 0 shift) 6 a 1 per shift (7 for 0 shift) 6 a 1 per shift (7 for 0 shift) 2 2 2 2 2 2 15 (includes fetch of configuration byte) 3 8 25 (proper key improper key)
14
M80C196KB
MEMORY MAP
0FFFFH EXTERNAL MEMORY OR I O 4000H INTERNAL ROM EPROM OR EXTERNAL MEMORY 2080H RESERVED 2040H UPPER 8 INTERRUPT VECTORS 2030H ROM EPROM SECURITY KEY 2020H RESERVED 2019H CHIP CONFIGURATION BYTE 2018H RESERVED 2014H LOWER 8 INTERRUPT VECTORS PLUS 2 SPECIAL INTERRUPTS 2000H PORT 3 AND PORT 4 1FFEH EXTERNAL MEMORY OR I O 0100H INTERNAL DATA MEMORY - REGISTER FILE (STACK POINTER RAM AND SFRS) EXTERNAL PROGRAM CODE MEMORY
M80C196KB INTERRUPTS
Number INT15 INT14 INT13 INT12 INT11 INT10 INT09 INT08 NMI HSI FIFO Full EXTINT Pin TIMER2 Overflow TIMER2 Capture 4th Entry into HSI FIFO RI TI Source Vector Priority Location 203EH 203CH 203AH 2038H 2036H 2034H 2032H 2030H 2012H 2010H 200EH 200CH 200AH 2008H 2006H 2004H 2002H 2000H 15 14 13 12 11 10 9 8 NA NA 7 6 5 4 3 2 1 0
SPECIAL Unimplemented Opcode SPECIAL Trap INT07 INT06 INT05 INT04 INT03 INT02 EXTINT Serial Port Software Timer HSI 0 Pin High Speed Outputs HSI Data Available A D Conversion Complete Timer Overflow
0000H
INT01 INT00
ROM EPROM is available for the 80C196
19H 18H 17H 16H 15H 14H 13H 12H 11H 10H 0FH 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H
STACK POINTER IOS2 IOS1 IOS0 WSR INT MASK 1 INT PEND 1 SP STAT
19H 18H 17H 16H 15H 14H 13H 12H 11H 10H 0FH 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H WSR e 0
STACK POINTER PWM CONTROL IOC1 IOC0 WSR INT INT SP MASK 1 PEND 1 CON
PORT2 PORT1 PORT0 TIMER2 (HI) TIMER2 (LO) TIMER1 (HI) TIMER1 (LO) INT PENDING INT MASK SBUF(RX) HSI STATUS HSI TIME (HI) HSI TIME (LO) AD AD RESULT (HI) RESULT (LO)
PORT2 PORT1 BAUD RATE TIMER2 (HI) TIMER2 (LO) IOC2 WATCHDOG INT INT PENDING MASK OTHER SFRS IN WSR 15 BECOME READABLE IF THEY WERE WRITABLE IN WSR e 0 AND WRITABLE IF THEY WERE READABLE IN WSR e 0 0FH 0EH 0DH 0CH RESERVED (1) RESERVED (1) T2 CAPTURE (HI) T2 CAPTURE (LO) WSR e 15
SBUF(TX) HSO HSO HSO HSI AD COMMAND TIME (HI) TIME (LO) MODE COMMAND
ZERO REG (HI) ZERO REG (LO) WHEN READ
ZERO REG (HI) ZERO REG (LO) WHEN WRITTEN
NEW OR CHANGED REGISTER FUNCTION NOTE 1 Reserved registers should not be written
15
M80C196KB
USING THE ALTERNATE REGISTER WINDOW (WSR e 15)
I O register expansion on the new CHMOS members of the MCS-96 family has been provided by making two register windows available Switching between these windows is done using the Window Select Register (WSR) The PUSHA and POPA instructions can be used to push and pop the WSR and second interrupt mask when entering or leaving interrupts so it is easy to change between windows On the M80C196KB only Window 0 and Window 15 are active Window 0 is a true superset of the standard 8096 SFR space while Window 15 allows the read-only registers to be written and write-only registers to be read The only major exception to this is the Timer2 register which is the Timer2 capture register in Window 15 The writeable register for Timer2 is in Window 0 There are also some minor changes and cautions The descriptions of the registers which have different functions in Window 15 than in Window 0 are listed below AD COMMAND (02H) AD RESULT (02H 03H) HSI MODE (03H) HSI TIME (04H 05H) HSO TIME (04H 05H) HSI STATUS (06H) HSO COMMAND (06H) SBUF(RX) (07H) SBUF(TX) (07H) WATCHDOG(0AH) TIMER1 (0AH 0BH) TIMER2 (0CH 0DH) IOC2 (0BH) BAUD RATE (0EH) PORT0 (0EH) PORT1 SP STAT (11H) SP CON (11H) IOS0 (15H) IOC0 (15H) IOS1 (16H) IOC1 (16H) IOS2 (17H) PWM CONTROL (17H) Read the last written command Write a value into the result register Read the value in HSI MODE Write to FIFO Holding register Read the last value placed in the holding register Write to status bits but not to HSI pin bits (Pin bits are 1 3 5 7) Read the last value placed in the holding register Write a value into the receive buffer Read the last value written to the transmit buffer Read the value in the upper byte of the WDT Write a value to Timer1 Read Write the Timer2 capture register Note that Timer2 read write is done with WSR e 0 Last written value is readable except bit 7 (note 1) No function cannot be read No function no output drivers on the pins Register reserved IOPORT1 cannot be read or written in Window 15 Register reserved Set the status bits TI and RI can be set but it will not cause an interrupt Read the current control byte Writing to this register controls the HSO pins Bits 6 and 7 are inactive for writes Last written value is readable except bit 1 (note 1) Writing to this register will set the status bits but not cause interrupts Bits 6 and 7 are not functional Last written value is readable Writing to this register will set the status bits but not cause interrupts Read the duty cycle value written to PWM CONTROL
NOTE 1 IOC2 7 (CAM CLEAR) and IOC0 1 (T2RST) are not latched and will read as a 1 (precharged bus) Being able to write to the read-only registers and vice-versa provides a lot of flexibility One of the most useful advantages is the ability to set the timers and HSO lines for initial conditions other than zero Reserved registers may be used for testing as future features Do not write to these registers Read from reserved registers will return indeterminate values
16
M80C196KB
SFR BIT SUMMARY
A summary of the SFRs which control I O functions has been included in this section The summary is separated into a list of those SFRs which have changed on the M80C196KB and a list of those which have remained almost the same The following M80C196KB SFRs are different than those on the M8096BH (The Read and Write comments indicate the register's function in Window 0 unless otherwise specified ) SBUF(TX) 07h write BAUD RATE 0Eh write SP STAT Now double buffered
Uses new Baud Rate Values
7 RB8 RPE
6 RI
5 TI
4 FE
3 TXE
2 OE
1 X
0 X
11h read
RPE RI TI FE TXE OE
Receive Parity Error Receive Indicator Transmit Indicator Framing Error Transmitter Empty Receive Overrun Error
IPEND1 IMASK1
7
6
5
4
3
2
1 RI
0 TI
FIFO EXT T2 T2 NMI HSI4 FULL INT OVF CAP
12h 13h read write
NMI Non-Maskable Interrupt (set to 0 for future compatibility) FIFO FULL HSIO FIFO full EXTINT T2OVF T2CAP HSI4 RI TI External Interrupt Pin Timer2 Overflow Timer2 Capture HSI has 4 or more entries in FIFO Receive Interrupt Transmit Interrupt
17
M80C196KB
WSR 14h read write
7 0
6 0
5 0
4 0
3 W
2 W
1 W
0 W
WWWW e 0 WWWW e 14 WWWW e 15 0000
SFRs function like a superset of M8096 SFRs PPW register Exchange read write registers Undefined do not use These bits must always be written as zeros to provide compatibility with future products
WWWW e OTHER
IOS2
7
6
5
4
3
2
1
0
START T2 HSO 5 HSO 4 HSO 3 HSO 2 HSO 1 HSO 0 A2D RESET 17h read Indicates which HSO event occured START A2D T2RESET HSO 0-5 IOC2 7 6 5 4 A2D CPD HSO CMD 15 start A to D HSO CMD 14 Timer 2 reset Output pins HSO 0 through HSO 5 3 X 2 1 0 FAST T2EN
CLEAR ENA T2ALT CAM LOCK INT 0Bh write CLEAR CAM ENA LOCK T2ALT INT A2D CPD X SLOW
SLOW T2UD PWM ENA
Clear Entire CAM Enable lockable CAM entry feature Enable T2 Alternate Interrupt at 8000H Clock Prescale Disable for low XTAL frequency (A to D conversion in fewer state times) Set to 0 Turn on divide by 2 Prescaler on PWM Enable Timer 2 as up down counter Enable Fast increment of T2 once per state time
PWM
T2UD ENA FAST T2EN
The following registers are the same on the M80C196KB as they were on the M8096BH
A D Result LO (02H) A D Command (02H)
271089 -4
271089 - 5
18
M80C196KB
Chip Configuration (2018H)
HSI Mode (03H)
271089 -6 Minor Change
271089 - 7
HSI
Status (06H)
HSO Command (06H)
271089 -8 271089 - 9 Minor Change
SPCON (11H)
IOS0 (15H)
271089 - 10
271089 - 11
19
M80C196KB
IOC0 (15H)
Port 2 Multiple Functions Pin 20 21 23 24
271089 - 12
Func Output Input Input Input Output QBD QBD
Alternative Function TXD (Serial Port Transmit) RXD (Serial Port Receive) T2CLK (Timer2 Clock Baud) T2RST (Timer2 Reset) PWM Output Timer2 up down select Timer2 Capture
Control Reg IOC1 5 SPCON 3 IOC0 7 IOC0 5 IOC1 0 IOC2 1 NA
25 26
IOS1 (16H)
27
QBD e Quasi-bidirectional
Baud Rate Calculations
Asynchronous Modes 1 2 and 3
Baud Reg e T2CLK XTAL1 b 1 OR Baud Rate c 16 Baud Rate c 8
271089 - 13
Synchronous Mode 0
Baud Reg e T2CLK XTAL1 b 1 OR Baud Rate c 2 Baud Rate
IOC1 (16H)
Baud Rates and Baud Register Values Baud Rate 300 1200 2400 4800 9600 19 2K
271089 - 14
XTAL Frequency 8 0 MHz 10 0 MHz 12 0 MHz 0 00 0 00 b 0 16 0 16 0 16 0 16
1666 b 0 02 2082 0 02 2499 416 b 0 08 520 b 0 03 624 207 103 51 25 0 16
b 0 16 b 0 16
0 16
259 129 64 32
0 16 0 16 0 16 1 40
312 155 77 38
Baud Register Value % Error A maximum baud rate of 750 Kbaud is available in the asynchronous modes with 12 MHz on XTAL1 The synchronous mode has a maximum rate of 3 0 Mbaud with a 12 MHz clock Location 0EH is the Baud Register It is loaded sequentially in two bytes with the low byte being loaded first This register may not be loaded with zero in serial port Mode 0 NOTE The maximum T2CLK rate is 3 MHz when used to set the baud rate
20
M80C196KB
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Voltage On Any Pin to VSS Power Dissipation
b 55 C to a 125 C b 65 C to a 150 C b 0 5V to a 7 0V
NOTICE This data sheet contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design
1 5W
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
OPERATING CONDITIONS MIL-STD-883
Symbol TC VCC VREF fOSC Description Case Temperature (Instant On) Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min
b 55
Max
a 125
Units C V V MHz
4 50 4 50 35
5 50 5 50 12
Military Temperature (MTO)
Symbol TC VCC VREF fOSC Description Case Temperature (Instant On) Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min
b 55
Max
a 125
Units C V V MHz
4 50 4 50 35
5 50 5 50 12
NOTE ANGND and VSS should be nominally at the same potential
DC Characteristics
Symbol VIL VIH VIH1 VIH2 VOL
(Over Specified Operating Conditions) Description Min
b0 5
Max 08 VCC VCC VCC 03 0 45 15
Units V V V V V V V V V V V V V
Comments
Input Low Voltage Input High Voltage (Note 1) Input High Voltage on XTAL 1 Input High Voltage on RESET Output Low Voltage
0 2 VCC a 1 0 0 7 VCC 22
IOL e 200 mA IOL e 3 2 mA IOL e 7 mA IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 mA IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA
VOH
Output High Voltage (Standard Outputs) (Note 2) Output High Voltage (Quasi-bidirectional Outputs) (Note 3)
VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 3 VCC b 0 7 VCC b 1 5
VOH1
NOTES 1 All pins except RESET and XTAL1 2 Standard Outputs include AD0-15 RD WR ALE BHE INST HSO pins PWM P2 5 CLKOUT RESET Ports 3 and 4 TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open-drain outputs 3 QBD (Quasi-bidirectional) pins include Port 1 P2 6 and P2 7
21
M80C196KB
DC Characteristics
Symbol ILI ILI1 ITL IIL IIL1 ICC IREF IIDLE ICC1 IPD RRST CS
(Over Specified Operating Conditions) (Continued) Description Min Max
g10 g7
Units mA mA mA mA mA mA mA mA mA mA X pF
Comments 0 k VIN k VCC b 0 3V 0 k VIN k VREF VIN e 2 0V VIN e 0 45V VIN e 0 45 V XTAL1 e 12 MHz VCC e VPP e VREF e 5 5V
Input Leakage Current (Std Inputs) (Note 4) Input Leakage Current () 1 to 0 Transition Current (QBD Pins) (Note 3) Logical 0 Input Current (QBD Pins) (Note 3) Logical 0 Input Current in Reset (Note 5) (ALE RD WR BHE INST P2 0) Active Mode Current in Reset A D Converter Reference Current Idle Mode Current Active Mode Current Powerdown Mode Current Reset Pullup Resistor Pin Capacitance (Any Pin to VSS) 6K
b 800 b 50 b 850
60 5 25 30 50 50K 10
XTAL1 e 3 5 MHz VCC e VPP e VREF e 5 5V XTAL1 e 12 MHz
fTEST e 1 0 MHz
NOTES (Notes apply to all specifications) 2 Standard Outputs include AD0-15 RD WR ALE BHE INST HSO pins PWM P2 5 CLKOUT RESET Ports 3 and 4 TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open-drain outputs 3 QBD (Quasi-bidirectional) pins include Port 1 P2 6 and P2 7 4 Standard Inputs include HSI pins EA READY BUSWIDTH NMI RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 5 Holding these pins below VIH in Reset may cause the part to enter test modes 6 Maximum current per pin must be externally limited to the following values if VOL is held above 0 45V or VOH is held below VCC b 0 7V IOL on Output pins 10 mA IOH on quasi-bidirectional pins self limiting IOH on Standard Output pins 10 mA 7 Maximum current per bus pin (data and control) during normal operation is g3 2 mA 8 During normal (non-transient) conditions the following total current limits apply IOH is self limiting Port 1 P2 6 IOL 29 mA IOH 26 mA HSO P2 0 RXD RESET IOL 29 mA IOL 13 mA IOH 11 mA P2 5 P2 7 WR BHE IOH 52 mA AD0 - AD15 IOL 52 mA IOH 13 mA RD ALE INST-CLKOUT IOL 13 mA
271089 - 16
Figure 4 ICC and IIDLE vs Frequency 22
M80C196KB
AC Characteristics
(Over Specified Operating Conditions) Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns fOSC e 12 MHz The system must meet these specifications to work with the M80C196KB Symbol TAVYV TLLYV TYLYH TCLYX TLLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRXDX Description Address Valid to READY Setup ALE Low to READY Setup M80C196KB Non READY Time READY Hold after CLKOUT Low READY Hold after ALE Low Address Valid to Buswidth Setup ALE Low to Buswidth Setup Buswidth Hold after CLKOUT Low Address Valid to Input Data Valid M80C196KB RD Active to Input Data Valid M80C196KB CLKOUT Low to Input Data Valid End of RD to Input Data Float Data Hold after RD Inactive 0 0 3TOSC b 67 TOSC b 23 TOSC b 50 TOSC b 20 0 TOSC b 15 Min Max 2TOSC b 85 TOSC b 75 No upper limit TOSC b 30 2TOSC b 40 2TOSC b 85 TOSC b 70 Units ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) Notes
NOTE 1 If max is exceeded additional wait states will occur
23
M80C196KB
AC Characteristics
(Over Specified Operating Conditions) (Continued) Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns fOSC e 12 MHz The M80C196KB will meet these specifications Symbol FXTAL TOSC TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX Description Frequency on XTAL1 M80C196KB I FXTAL M80C196KB XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling Edge to ALE Rising ALE Falling Edge to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Falling Edge Address Hold after ALE Falling Edge ALE Falling Edge to RD Falling Edge RD Low to CLKOUT Falling Edge RD Low Period RD Rising Edge to ALE Rising Edge RD Low to Address Float ALE Falling Edge to WR Falling Edge CLKOUT Low to WR Falling Edge Data Stable to WR Rising Edge M80C196KB CLKOUT High to WR Rising Edge WR Low Period Data Hold after WR Rising Edge WR Rising Edge to ALE Rising Edge BHE INST HOLD after WR Rising Edge TOSC b 10 0 TOSC b 23
b5
Min 35 83 20 2TOSC TOSC b 10
b 10 b 15
Max 12 286 110
Units MHz ns ns ns ns ns ns ns ns ns ns ns
Notes
TOSC a 10 10 15
4TOSC TOSC b 12 TOSC b 20 TOSC b 40 TOSC b 40 4 TOSC b 5 TOSC TOSC a 25 10 25 TOSC a 12
ns ns ns ns ns (Note 2)
25
ns ns
15
ns ns ns
TOSC b 30 TOSC b 15 TOSC b 15 TOSC b 15 TOSC a 10
ns ns
(Note 2)
NOTE 2 Assuming back-to-back bus cycles
24
M80C196KB
System Bus Timings
271089 - 17
271089 - 18
25
M80C196KB
EXTERNAL CLOCK DRIVE
Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency M80C196KB Oscillator Period M80C196KB High Time Low Time Rise Time Fall Time Min 35 83 32 32 10 10 Max 12 0 286 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE WAVEFORMS
271089 - 19
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
271089 - 20 AC Testing inputs are driven at 2 4V for a Logic ``1'' and 0 45V for a Logic ``0'' Timing measurements are made at 2 0V for a Logic ``1'' and 0 8V for a Logic ``0''
271089 - 21 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when a 100 mV change from the Loaded VOH VOL Level occurs IOL IOH e g15 mA
EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ``T'' for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points Conditions Signals H L V X Z High Low Valid No Longer Valid Floating A - Address B - BHE C - CLKOUT D - DATA G - Buswidth L - ALE ADV R W X Y RD WR WRH WRL XTAL1 READY
26
M80C196KB
AC CHARACTERISTICS
SERIAL PORT TIMING Symbol TXLXL TXLXH TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
SERIAL PORT
SHIFT REGISTER MODE
SHIFT REGISTER MODE Parameter Min 6 TOSC 4 TOSC b 50 4 TOSC 2 TOSC b 50 2 TOSC b 50 2 TOSC b 50 2 TOSC a 50 TOSC a 50 0 TOSC 2 TOSC a 50 4 TOSC a 50 Max Units ns ns ns ns ns ns ns ns ns ns
Serial Port Clock Period (BRR t 8002H) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) Serial Port Clock Period (BRR e 8001H) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float
WAVEFORM
SERIAL PORT
SHIFT REGISTER MODE
SERIAL PORT WAVEFORM
SHIFT REGISTER MODE
271089 - 22
27
M80C196KB
stability of VREF VREF must be close to VCC since it supplies both the resistor ladder and the digital section of the converter
A TO D CHARACTERISTICS
There are two modes of A D operation with or without clock prescaler The speed of the A D converter can be adjusted by setting a clock prescaler on or off At high frequencies more time is needed for the comparator to settle The maximum frequency with the clock prescaler disabled is 8 MHz The conversion times with the prescaler turned on or off is shown in the table below The converter is ratiometric so the absolute accuracy is directly dependent on the accuracy and Clock Prescaler On IOC2 4 e 0 Mode 0-158 States 26 33 ms 12 MHz
A D CONVERTER SPECIFICATIONS
The specifications given below assume adherence to the Operating Conditions section of this data sheet Testing is performed in Mode 2 with VREF e 5 12V and 12 MHz on XTAL1
Clock Prescaler Off IOC2 4 e 1 Mode 2 - 91 States 22 75 ms 8 MHz
A D CHARACTERISTICS
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Sample Time Slow Mode Fast Mode Input Capacitance
(Over Specified Operating Conditions) Typical (1) Minimum 256 0
b 0 5 g0 5
g0 5
Maximum 1024 10
g4
Units Levels Bits LSBs LSBs LSBs
Notes
0 0 0
g0 25
g4 g2 g1
LSBs LSBs LSBs LSBs LSB C LSB C LSB C
0 009 0 009 0 009
b 60 b 60 b 60
dB dB dB
23 2 2
750 0 15 8 3
1 2K 30
X mA States States pF 4 4
NOTES An ``LSB'' as used here has a value of approximately 5 mV 1 These values are expected for most parts at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer Break-Before-Make Guaranteed 4 One state e 167 ns at 12 MHz 250 ns at 8 MHz
28
M80C196KB
IDEAL CHARACTERISTIC A characteristic with its first code transition at VIN e 0 5 LSB its last code transition at VIN e (VREF b 1 5 LSB) and all code widths equal to one LSB INPUT RESISTANCE The effective series resistance from the analog input pin to the sample capacitor LSB Least Significant Bit The voltage corresponding to the full scale voltage divided by 2n where n is the number of bits of resolution of the converter For an 8-bit converter with a reference voltage of 5 12V one LSB is 20 mV Note that this is different than digital LSBs since an uncertainty of two LSB when referring to an A D converter equals 40 mV (This has been confused with an uncertainty of two digital bits which would mean four counts or 80 mV ) NON-LINEARITY The maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal characteristic OFF-ISOLATION Attenuation of a voltage applied on a deselected channel of the A D converter (Also referred to as Crosstalk ) REPEATABILITY The difference between corresponding code transitions from different actual characteristics taken from the same converter on the same channel at the same temperature voltage and frequency conditions RESOLUTION The number of input voltage levels that the converter can unambiguously distinguish between Also defines the number of useful bits of information which the converter can return SAMPLE TIME Begins when the sample capacitor is attached to a selected channel and ends when the sample capacitor is disconnected from the selected channel TEMPERATURE COEFFICIENTS Change in the stated variable per degree centigrade temperature change Temperature coefficients are added to the typical values of a specification to see the effect of temperature drift TERMINAL BASED CHARACTERISTIC An actual characteristic which has been rotated and translated to remove zero offset and full scale error VCC REJECTION Attenuation of noise on the VCC line to the A D converter ZERO OFFSET The difference between the expected and actual input voltage corresponding to the first code transition 29
A D GLOSSARY OF TERMS
ABSOLUTE ERROR The maximum difference between corresponding actual and ideal code transitions Absolute Error accounts for all deviations of an actual converter from an ideal converter ACTUAL CHARACTERISTIC The characteristic of an actual converter The characteristic of a given converter may vary over temperature supply voltage and frequency conditions An actual characteristic rarely has ideal first and last transition locations or ideal code widths It may even vary over multiple conversions under the same conditions BREAK-BEFORE-MAKE The property of multiplexer which guarantees that a previously selected channel will be deselected before a new channel is selected (e g the converter will not short inputs together) CHANNEL-TO-CHANNEL MATCHING The difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature voltage and frequency conditions CHARACTERISTIC A graph of input voltage versus the resultant output code for an A D converter It describes the transfer function of the A D converter CODE The digital value output by the converter
CODE TRANSITION The point at which the converter changes from an output code of Q to a code of Q a 1 The input voltage corresponding to a code transition is defined to be that voltage which is equally likely to produce either of two adjacent codes CODE WIDTH The voltage corresponding to the difference between two adjacent code transitions DC INPUT LEAKAGE Leakage current to ground from an analog input pin DIFFERENTIAL NON-LINEARITY The difference between the ideal and actual code widths of the terminal based characteristic FEEDTHROUGH Attenuation of a voltage applied on the selected channel of the A D Converter after the sample window closes FULL SCALE ERROR The difference between the expected and actual input voltage corresponding to the full scale code transition
M80C196KB
M80C196KB FUNCTIONAL DEVIATIONS
The M80C196KB has the following problems 1 The DJNZW instruction is guaranteed to be functional The DJNZ (byte instruction) work around is no longer needed 2 The serial port only tolerates a a 1 25% b 7 5% baud rate error between Transmitter and Receiver If the serial port fails on the receiver increase the baud rate 3 The HSI unit has two errata one dealing with resolution and the other with first entries into the FIFO The HSI resolution is 9 states instead of 8 states Events on the same line may be lost if they occur faster than once every 9 state times There is a mismatch between the 9 state time HSI resolution and the 8 state time timer This causes one time value to be unused every 9 timer counts Events may receive a time-tag one count later than expected because of this ``skipped'' time value If the first two events into an empty FIFO (not including the Holding Register) occur in the same internal phase both are recorded with one timetag Otherwise if the second event occurs within 9 states after the first its time-tag is one count later than the first's If this is the ``skipped'' time value the second event's time-tag is 2 counts later than the first's If the FIFO and Holding Register are empty the first event will transfer into the Holding Register after 8 state times leaving the FIFO empty again If the second event occurs after this time it will act as a new first event into an empty FIFO 4 The serial port Framing Error flag that failed to indicate an error if the bit preceding the stop bit is a 1 has been fixed
CONVERTING FROM OTHER M8097 FAMILY PRODUCTS TO THE M80C196KB
The following list of suggestions for designing an M809XBH system will yield a design that is easily converted to the M80C196KB 1 Do not base critical timing loops on instruction or peripheral execution times 2 Use equate statements to set all timing parameters including the baud rate 3 Do not base hardware timings on CLKOUT or XTAL1 The timings of the M80C196KB are different than those of the M8X9XBH but they will function with standard ROM EPROM Peripheral type memory systems 4 Make sure all inputs are tied high or low and not left floating 5 Indexed and indirect operations relative to the stack pointer (SP) work differently on the M80C196KB than on the M8097 On the M8097 the address is calculated based on the un-updated version of the stack pointer The M80C196KB uses the updated version The offset for PUSH SP POP SP PUSH nn SP and POP nn SP instructions may need to be changed by a count of 2
30

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